Saturable loop core current source

ABSTRACT

A low-power, regulated, high-impedance current source wherein a saturable or square loop core is used to control the current in an inhibit winding of a ferrite core-type computer memory circuit.

United States Patent BIAS CURRENT CONTROL SIGNAL Bruder Mar. 14, 1972 [54] SATURABLE LOOP CORE CURRENT [56] References Cited SOURCE [72] Inventor: John F. Bruder, Phoenix, Ariz. UNITED STATES PATENTS 3,193,691 7/1965 Akmenkalns ..340/174 TB [73] Ass'gnee' gif g' fl i 'f g fl' fi 3,140,400 7/1964 Shansky et a]. ....3o7/ss MP y 2,882,482 4/1959 Simkins ..323/7 I 1 1970 3,193,693 7/1965 Daykin ..307/ss MP [2|] App]. No.: 95,647

Primary Examiner-A. D. Peilmen i A -R. S. Sciasc' d E. H d 6S 52 us. c1. ..323/6, 323/56, 340/166C o g [51] Int. Cl. G0 3/08 581 Field of Search ..'....307/ss MP, 106, 314; 323/1, [57] ABSTRACT .1 323/4, 6, 7, 8. 56, 3 340/ 165 C, A low-power, regulated, high-impedance current source 174 TB wherein a saturabie or square loop core is used to control the current in an inhibit winding of a ferrite core-type computer memory circuit.

3 Claims 1 Drawing Figure PATENTEDMIIR I4 I972 3,649,904

+l5V +l5V- INHIBIT I I WINDING 0 W4 l W2 W3 BIAS CURRENT CONTROL SIGNAL IN V EN TOR.

I HN F. BRUDE R BY fi ATTORNEY BACKGROUND OF THE INVENTION In the field of computer memory circuits of the ferrite core type current in an inhibit winding is used to prevent the change of state of a particular core due to the current in a write" winding. The values of these currents must be closely controlled so that an accidental change of state of a particular core does not occur. The control of these currents is usually accomplished by a sophisticated transistor regulator circuit. Since one regulator circuit is required per inhibit winding in a core matrix, this approach is initially expensive, increases the power needed to operate the computer memory, and the reliability of the computer memory is reduced as active elements are employed in the regulator circuit.

It is an object of this invention to eliminate the need for a separate transistorregulating circuit for each inhibit circuit in a core matrix.

It is another object of this invention to provide a regulating circuit which returns at least a portion of the energy employed during operation to the power supply.

Still another object of the present invention is to provide a regulating circuit having a minimum number of active components.

These and other objects of the present invention will become apparent from the following description.

SUMMARY OF THE INVENTION The present invention provides a low-power, regulated, high-impedance circuit for control of the current in the inhibit winding of a core type memory. The regulator employes a saturable or square loop core transformer as the control element.

DESCRIPTION OF THE DRAWING The FIG. is a schematic diagram of the regulator circuit of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT As seen in the drawing, the main elements of the regulator include the inhibit winding W transformer T,, saturable core transformer T transistor 0,, and the plus and minus l5-volt power supplies (not shown).

In operation, a bias current I is applied to the winding W of the saturable core transformer T via L,. The magnitude of the bias current is such that saturation of one leg of the core of T is maintained. When a current is to be applied to the inhibit winding W,, the transistor Q, is driven into conduction by an appropriate control signal applied to the base of Q,. The current I, begins to flow and the flux generated thereby cancels the flux in the core of T generated by the bias current 1,. As the currents I, and I become equal, the core of T comes out of saturation because the flux in the core is now near zero. When the core of T comes out of saturation, it begins to exhibit a high permeability and the reactance of the winding W, limits the current I, to a value that balances out the bias current I Since I, also flows through T,, a current is induced in the W, winding of T, and hence in the inhibit winding W By selecting proper component values, this balance condition can be made the regulated current level of the pulse current desired in the inhibit winding W When current is no longer desired in the inhibit winding, the control signal applied to the base of Q, is removed, Q, becomes nonconductive and the current I, goes to zero. Simultaneously the energy that is stored in the saturable core of T is restored to the l5-volt power supply via C W and C C and W restore the energy stored in the inhibit winding and the transformer T, to the +15-volt power supply. Hence most of the reactive energy built up in the magnetic fields of the transformers during the operation of the regulator is returned to the power supplies, thereby improving the efiiciency of the regulator. Since I, is

now zero, the bias current], drive the core of T, back into saturation and the circuit 15 capable of repeating the above described cycle.

It is understood that the foregoing disclosure relates only to the preferred embodiment of the present invention and any modifications obvious to one skilled in the art, which do not depart from the spirit and scope of the invention as set forth in the following claims, are deemed to constitute a part of this disclosure.

What is claimed is:

1. A high-impedance current-regulating circuit for controlling the current in the inhibit winding of a ferrite core memory matrix and a power source for energizing said circuit comprising:

first transformer means for inducing a control current in the inhibit winding of the core matrix;

second transformer means of the saturable core type serially connected to the first transformer means for regulating the current in the first transformer means; bias means connected to the second transformer means for maintaining the core of said second transformer means in a saturated condition;

transistor means serially connected to the second transformer means for controlling the flow of current in said second transformer; and

energy restoring means for restoring the energy in the magnetic field of the transformer back to the power source.

2. A regulating circuit as defined in claim I wherein the seria] connection between the first and second transformer means joins the input windings of the first transformer means to the input winding of the second transformer means such that regulation of the current in the second transformer means also regulates the current in the first transformer means.

3. A regulating circuit as defined in claim 1 wherein said transistor means is serially connected to the input winding of said second transformer means for initiating and stopping the current in said winding. 

1. A high-impedance current-regulating circuit for controlling the current in the inhibit winding of a ferrite core memory matrix and a power source for energizing said circuit comprising: first transformer means for inducing a control current in the inhibit winding of the core matrix; second transformer means of the saturable core type serially connected to the first transformer means for regulating the current in the first transformer means; bias means connected to the second transformer means for maintaining the core of said second transformer means in a saturated condition; transistor means serially connected to the second transformer means for controlling the flow of current in said second transformer; and energy restoring means for restoring the energy in the magnetic field of the transformer back to the power source.
 2. A regulating circuit as defined in claim 1 wherein the serial connection between the first and second transformer means joins the input windings of the first transformer means to the input winding of the second transformer means such that regulation of the current in the second transformer means also regulates the current in the first transformer means.
 3. A regulating circuit as defined in claim 1 wherein said transistor means is serially connected to the input winding of said second transformer means for initiating and stopping the current in said winding. 